1. Field of the Invention
The present invention relates to unity-gain, wide bandwidth, bipolar voltage-follower circuits and, in particular, to a voltage-follower that utilizes cascode circuitry and cancellation circuitry to provide a very-low input current.
2. Description of the Related Art
A voltage-follower is a circuit that interfaces a high-impedance circuit with a low-impedance load. For unity-gain, wide bandwidth, bipolar voltage-follower applications which require operation very close to ground and a very-low input current (very-high impedance), voltage-followers are commonly designed with PNP input transistor stages and input current cancellation circuitry.
FIG. 1 shows a schematic diagram of a conventional bipolar voltage-follower circuit 10 that illustrates a PNP input transistor stage and input current cancellation circuitry. As shown in FIG. 1, circuit 10 includes an input stage 12 that generates
an intermediate voltage signal V.sub.INTER and that sources an input base current I.sub.BASE1 in response to an input voltage signal V.sub.INPUT and an input stage bias current I.sub.BIAS1. The intermediate voltage signal V.sub.INTER is equivalent to the input voltage signal V.sub.INPUT plus a first offset voltage.
Input stage 12 includes a PNP transistor P1 that has its emitter connected to an intermediate node N.sub.INTER, its collector connected to ground GND, and its base connected to an input node N.sub.INPUT. As shown, transistor P1 is biased by the input stage bias current I.sub.BIASI which, in addition to the input voltage signal V.sub.INPUT, causes the input base current I.sub.BASE1 to be generated by transistor P1.
Circuit 10 further includes an output stage 14 that generates an output voltage signal V.sub.OUT and that sinks a portion of the input stage bias current as an output base current I.sub.BASE0 in response to the intermediate voltage signal V.sub.INTER and an output bias current I.sub.BIASO. The output voltage signal V.sub.OUT is equivalent to the intermediate voltage signal V.sub.INTER minus a second offset voltage.
Output stage 14 includes a NPN transistor Q4 that has its emitter connected to an output node N.sub.OUT, its collector connected to a power supply Vcc, and its base connected to the intermediate node N.sub.INTER. As shown, transistor Q4 is biased by the output bias current I.sub.BIAS0 which, in addition to the intermediate voltage V.sub.INTER, causes the output base current I.sub.BASE0 to be sunk from the intermediate node N.sub.INTER by transistor Q4.
Transistors P1 and Q4 are both configured to operate as emitter-followers. In an emitter-follower configuration, the voltage at the base of a transistor is reproduced at its emitter plus or minus the voltage across its emitter-base junction, depending on whether a PNP or a NPN transistor is utilized, respectively. Thus, transistor P1 generates the intermediate voltage signal V.sub.INTER which is equivalent to the input voltage signal V.sub.INPUT plus a first offset voltage which is equivalent to the emitter-base voltage of transistor P1. Similarly, transistor Q4 generates the output voltage V.sub.OUT which is equivalent to the intermediate voltage V.sub.INTER less a second offset voltage which is equivalent to the base-emitter voltage of transistor Q4.
Thus, the second offset voltage is substantially equivalent to the first offset voltage. This allows the first and second offset voltages to effectively cancel each other out, thereby producing a voltage-follower with substantially no D.C. voltage level shift.
Circuit 10 further includes an input biasing stage 16 that generates the input stage bias current I.sub.BIASI and a tracking bias current I.sub.BIAST. Input biasing stage 16 includes three substantially identical PNP transistors P2, P3, and P4.
Transistor P4 has its emitter connected to a power supply VCC through a resistor R3, its collector connected to ground GND through a resistor R6, and its base connected to its collector. Transistor P2 has its emitter connected to power supply VCC through a resistor R1, its collector connected to the intermediate node N.sub.INTER, and its base connected to the collector of transistor P4. Similarly, transistor P3 has its emitter connected to power supply VCC through a resistor R2, its collector connected to a tracking node N.sub.T, and its base connected to the collector of transistor P4.
Transistors P2, P3, and P4, and resistors R1, R2, and R3 are configured as a current mirror. As stated above, in a current mirror configuration, the base-emitter voltages of two or more identical transistors are forced to be equal. This in turn forces the collector currents sourced by the two or more transistors to be equal.
P4 is a quasi-diode-connected input device which, along with resistor R6, sets a first fixed current I.sub.FIXED1. Transistors P2 and P3 are output devices whose collector currents are intended to match the first fixed current I.sub.FIXED1 flowing through R6. Thus, both the input stage bias current I.sub.BIASI and the tracking bias current I.sub.BIAST are substantially equivalent to each other and to the first fixed current I.sub.FIXED1.
Resistors R1, R2 and R3 establish emitter degeneration. The resistors are equal in value and type and thus match each other precisely, thereby aiding in the accuracy of the current mirror.
Referring again to FIG. 1, circuit 10 additionally includes an output biasing stage 20 that generates the output bias current I.sub.BIAS0. Output biasing stage 20 includes two substantially identical NPN transistors Q6 and Q7. Transistor Q7 has its emitter connected to ground GND through a resistor R9, its collector connected to power supply VCC through a resistor R11, and its base connected to its collector. Transistor Q7 is configured as a diode which, along with resistor R9, sets a second fixed current I.sub.FIXED2.
Transistor Q6 has its emitter connected to ground GND through a resistor R8, its collector connected to the output node N.sub.OUT, and its base connected to the collector of transistor Q7. Resistors R8 and R9 are equal in value and are utilized to improve the matching tolerances between transistors Q6 and Q7. Transistors Q6 and Q7 are also configured as a current mirror. Thus, transistor Q6 sinks output bias current I.sub.BIAS0 which is substantially equivalent to the second fixed current I.sub.FIXED2.
Circuit 10 further includes a cancellation stage 22 that sinks substantially all of the input base current I.sub.BASE1 in response to the tracking bias current I.sub.BIAST. Cancellation stage 22 includes three NPN transistors P5, Q1 and Q2. Transistor P5 has its emitter connected to the tracking node N.sub.T, its collector connected to ground GND, and its base connected to a third node N.sub.3. In addition, transistor P5 is formed to substantially match transistor P1.
Transistor Q2 has its emitter connected to ground GND through a resistor R5, it collector connected to the third node N.sub.3, and its base connected to its collector. Transistor Q1 is configured to match transistor Q2 and has its emitter connected to ground GND through a resistor R4, its collector connected to the base of transistor P1, and its base connected to the base of transistor Q2. Resistors R4 and R5 are substantially identical and are utilized to improve the matching tolerances between transistors Q1 and Q2.
Transistor Q2, which is configured as a diode, sets a tracking bias voltage V.sub.TB at the base of transistor P5. As stated above, since the tracking bias current I.sub.BIAST is substantially equivalent to the input stage bias current I.sub.BIAS1, transistors P5 and P1 are biased by substantially equivalent currents. Further, since transistors P5 and P1 are substantially equivalent, transistor P5 sources a tracking base current I.sub.BASET that is substantially equivalent to the input base current I.sub.BASET
In operation, the tracking base current I.sub.BASET flows into the collector of transistor Q2 and into the bases of transistors Q1 and Q2. Transistors Q1 and Q2, which are substantially identical, are configured as a current mirror. Since the base current sunk by transistors Q1 and Q2 is very small (transistors Q1 and Q2 are NPN transistors with a relatively high beta), the collector current of transistor Q2 is substantially equivalent to the tracking base current I.sub.BASET. Thus, transistor Q1 sinks a cancellation current I.sub.CAN which is substantially equivalent to the tracking base current I.sub.BASET. Therefore, since the cancellation current I.sub.CAN sunk by transistor Q1 is substantially equivalent to the tracking base current I.sub.BASET sourced by transistor P5, and since the tracking base current I.sub.BASET is substantially equivalent to the input base current I.sub.BASE1 sourced by transistor P1 (the tracking base current I.sub.BASET does not account for very slight variations in the input base current I.sub.BASE1 that result from variations of the input voltage signal V.sub.INPUT), then the cancellation current I.sub.CAN sunk by transistor Q1 is substantially equivalent to the input base current I.sub.BASE1 sourced by transistor P1. Therefore, cancellation stage 22 sinks substantially all of the input base current I.sub.BASE1.
As shown in FIB. 1, circuit 10 further includes a compensation stage 24 that sinks a portion of the tracking bias current I.sub.BIAST as a compensation base current I.sub.BASEC. The portion of the tracking bias current I.sub.BIAST sunk by compensation stage 24 is substantially equivalent to the portion of the input stage bias current I.sub.BIASI sunk by output stage 14.
Compensation stage 24 includes two NPN transistors Q3 and Q5. Transistor Q5 has its emitter connected to ground GND through a resistor R7, its collector connected to a fourth node N.sub.4, and its base connected to the base of transistor Q6. Transistor Q3 has its emitter connected to the fourth node N.sub.4, its collector connected to power supply VCC, and its base connected to the emitter of transistor P5.
Transistor Q5, along with transistors Q6 and Q7, is connected as a current mirror. Transistor Q5 sinks a compensation collector current I.sub.CC that is substantially equivalent to the output bias current I.sub.BIAS0. Thus, transistors Q3 and Q4 are substantially equivalently biased. Therefore, transistors Q3 and Q4 sink a substantially equivalent base current.
One problem with circuit 10 is the flucuation of the input stage bias current I.sub.BIAS1 in response to the input voltage signal V.sub.INPUT. When the input voltage signal V.sub.INPUT varies, the intermediate voltage signal V.sub.INTER and the collector voltage of transistor P2 correspondingly vary. As a result of its finite output impedance, the collector current of transistor P2 varies with the collector voltage and thus so would the magnitude of the input stage bias current I.sub.BIAS1.
On the other hand, since the collector of transistor P3 is not connected to the emitter of transistor P1, the collector voltage of transistor P3, and therefore the tracking bias current I.sub.BIAST, does not vary. Therefore, the tracking bias current I.sub.BIAST and the input stage bias current I.sub.BIAS1 are no longer substantially equivalent. Thus, there is a need for a circuit which can reduce the flucuations of the input stage bias current I.sub.BIAS1 when the input voltage signal V.sub.INPUT varies.
Another problem with circuit 10 is the increased emitter current, and thereby base current, sourced by transistor Q4 as a result of a variably resistive load. When a resistive load is connected to the output node N.sub.OUTPUT, the total current in the emitter of transistor Q4 is the sum of the output bias current I.sub.BIAS0 and the current sunk by the resistive load. Since the current in the emitter of transistor Q3 mirrors only the output bias current I.sub.BIAS0, the additional base current sunk by transistor Q4 as a result of the resistive load is not accounted for. Thus, there is a need for a circuit which can account for the additional current sunk as a result of a resistive load.